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74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
June 1993 Revised April 2005
74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The LVX574 is a high-speed octal D-type flip-flop which is controlled by an edge-triggered clock input (CP) and a buffered common Output Enable (OE) input. When the OE input is HIGH, the eight outputs are in a high impedance state. The LVX574 is functionally identical to the LVX374 but with inputs and outputs on opposite sides of the package. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.
Features
s Input voltage translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance
Ordering Code:
Order Number 74LVX574M 74LVX574SJ 74LVX574MTC Package Number M20B M20D MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names D0-D7 CP OE O0-O7 Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs Description
(c) 2005 Fairchild Semiconductor Corporation
DS500050
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74LVX574
Functional Description
The LVX574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.
Truth Table
Inputs Dn H L X CP Outputs OE L L H On H L Z

X
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVX574
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI
0.5V to 7.0V 20 mA 0.5V to 7V 20 mA 20 mA 0.5V to VCC 0.5V r25 mA r75 mA 65qC to 150qC
180 mW
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Input Rise and Fall Time ('t/'V) 2.0V to 3.6V 0V to 5.5V 0V to VCC
0.5V
DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO
40qC to 85qC
0 ns/V to 100 ns/V
0.5V VCC 0.5V
DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) Power Dissipation
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH HIGH Level Output Voltage VOL LOW Level Output Voltage IOZ IIN ICC 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 3.6 3.6 VCC 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 2.0 3.0 3.0 3.6 1.9 2.9 2.58 0.0 0.0 0.1 0.1 0.36 2.0 3.0 TA Min 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.48 0.1 0.1 0.44 V VIN VIH or VIL V
25qC
Typ Max
TA
40qC to 85qC
Min 1.5 2.0 2.4 0.5 0.8 0.8 Max
Units
Conditions
V
V VIN VIH or VIL IOH IOH IOH IOL IOL IOL VIN VOUT VIN VIN VIH or VIL VCC or GND 5.5V or GND VCC or GND
50 PA 50 PA 4 mA
50 PA 50 PA 4 mA
r0.25 r0.1
4.0
r2.5 r1.0
40.0
PA PA PA
Noise Characteristics (Note 3)
Symbol VOLP VOLV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage
tf 3 ns)
VCC (V) 3.3 3.3 3.3 3.3
TA Typ 0.5
25qC Limit 0.8
Units V V V V
CL (pF) 50 50 50 50
0.5
0.8
2.0 0.8
Note 3: (Input tr
3
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74LVX574
AC Electrical Characteristics (Note 4)
Symbol fMAX Parameter Maximum Clock Frequency tPLH tPHL Propagation Delay Time CP to On tPZL tPZH 3-STATE Output Enable Time 3.3 r 0.3 tPLZ tPHZ tW tS tH tOSHL tOSLH 3-STATE Output Disable Time CP Pulse Width Setup Time Dn to CP Hold Time Dn to CP Output to Output Skew (Note 4) 2.7 3.3 r 0.3 2.7 3.3 r 0.3 2.7 3.3 r 0.3 2.7 3.3 r 0.3 2.7 3.3
|tPLHm tPLHn|, tOSHL
VCC (V) 2.7 3.3 r 0.3 2.7 3.3 r 0.3 2.7 Min 60 45 80 50
TA
25qC
Typ 115 60 125 75 9.2 11.5 8.5 11.0 9.8 11.4 8.2 10.7 12.1 11.0 14.5 18.0 13.2 16.7 15.0 18.5 12.8 16.3 19.1 15.0 Max
TA
40qC to 85qC
Min 50 40 65 45 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 7.5 5.0 5.0 3.5 1.5 1.5 17.5 21.0 15.5 19.0 18.5 22.0 15.0 18.5 22.0 17.0 Max
Units CL MHZ CL CL CL CL ns CL CL CL CL ns CL CL CL ns ns ns ns CL CL
Conditions 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF, RL 50 pF, RL 15 pF, RL 50 pF, RL 50 pF, RL 50 pF, RL 1 k: 1 k: 1 k: 1 k: 1 k: 1 k:
6.5 5.0 5.0 3.5 1.5 1.5 1.5 1.5
|tPHLm tPHLn|.
1.5 1.5
ns
CL
50 pF
Note 4: Parameter guaranteed by design. tOSLH
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (Note 5)
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Parameter
TA Min
25qC
Typ 4 6 27 Max 10
TA
40qC to 85qC
Min Max 10
Units pF pF pF
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74LVX574
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
5
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74LVX574
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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